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| DATA SHEET PD178023,178024 8-BIT SINGLE-CHIP MICROCONTROLLER MOS INTEGRATED CIRCUIT DESCRIPTION The PD178023, 178024 are 8-bit single-chip CMOS microcontrollers containing hardware for digital tuning systems. These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for system control. As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In addition, three serial interfaces, I2C bus (IIC0), three-wire (SIO3), and UART are provided. Moreover, a flash memory model, the PD178F124, that operates in the same supply voltage range as the mask ROM models, and various development tools are also under development. For the detailed functional description, refer to the following User's Manuals: PD178024, 178124 Subseries User's Manual : U13915E 78K/0 Series User's Manual - Instruction : U12326E FEATURES * High-capacity ROM and RAM Item Part Number Program Memory (ROM) Data Memory Internal high-speed RAM 24K bytes 32K bytes 1024 bytes PD178023 PD178024 * Instruction cycle: fX = 4.5 MHz) 0.45/0.89/1.78/3.56/7.11 s (with crystal resonator of * Hardware for PLL frequency synthesizer * Vectored interrupt sources: * Supply voltage phase comparator, charge pump 17 Dual modulus prescaler, programmable divider, * Many internal hardware units General-purpose I/O ports, A/D converter, serial interface (I2C bus and UART mode), timers, frequency :VDD = 4.5 to 5.5 V (during PLL and CPU operations) counter, power-ON clear circuit :VDD = 3.5 to 5.5 V (during CPU operation) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14126EJ1V0DS00 (1st edition) Date Published September 1999 N CP(K) Printed in Japan (c) 1999 PD178023, 178024 APPLICATION FIELD Car stereos ORDERING INFORMATION Part Number Package 80-pin plastic QFP (14 x 20 mm, 0.8-mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic QFP (14 x 20 mm, 0.8-mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) PD178023GF-xxx-3B9 PD178023GC-xxx-8BT PD178024GF-xxx-3B9 PD178024GC-xxx-8BT Remark xxx indicates ROM code suffix, which is Exx when the I2C bus is used. 2 Data Sheet U14126EJ1V0DS00 PD178023, 178024 DEVELOPMENT OF 8-BIT DTS SERIES Models under mass production Models under development Flash memory model or PROM model Mask ROM model 64/80 pins PD178F048 Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel 64/80 pins PD178048 subseries Internal OSD controller 8-bit PWM x 4 channels 14-bit PWM x 1 channel 100 pins PD178098 subseries Internal IEBus controller 100 pins PD178F098 Internal IEBusTM controller and UART 100 pins PD178078 subseries Internal UART 80 pins PD178F134 Internal LCD and UART 80 pins PD178034 subseries Internal LCD and UART 80 pins PD178F124 Internal UART 80 pins PD178024 subseries Internal UART 80 pins PD178018A subseries 80 pins PD178P018A 80 pins PD178003 subseries Limits functions of PD178018A subseries Data Sheet U14126EJ1V0DS00 3 PD178023, 178024 FUNCTIONAL OUTLINE (1/2) Item Internal memory ROM 24 Kbytes (Mask ROM) 1024 bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) 0.45 s/0.89 s/1.78 s/3.56 s/7.11 s (with crystal resonator of fX = 4.5 MHz) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. : 62 pins : 53 pins : 6 pins PD178023 32 Kbytes (Mask ROM) PD178024 High-speed RAM General-purpose register Minimum instruction execution time Instruction set I/O port Total * CMOS I/O * CMOS input * N-ch open-drain output : 3 pins A/D converter Serial interface 8-bit resolution x 6 channels (VDD = 4.5 to 5.5 V) * I2C bus modeNote : 1 channel * 3-wire mode : 1 channel * UART mode : 1 channel * Basic timer (timer carry FF (10 Hz)) : 1 channel * 8-bit timer/event counter : 2 channels * Watchdog timer Buzzer output Vectored interrupt source Maskable : 1 channel Timer 1 channel (1 kHz, 1.5 kHz, 3 kHz, 4 kHz) Internal : 11 External: 5 Internal: 1 Internal: 1 2 types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOL and VCOH pins) Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz) Error out output: 2 pins Unlock detectable in software Non-maskable Software PLL frequency synthesizer Division mode Reference frequency Charge pump Phase comparator Note When the I2C bus mode is used (including when the mode is implemented in software without using the peripheral hardware), consult NEC when ordering a mask. 4 Data Sheet U14126EJ1V0DS00 PD178023, 178024 (2/2) Item Frequency counter PD178023 Frequency measurement * AMIFC pin: For 450-kHz counting * FMIFC pin: For 450-kHz/10.7-MHz counting PD178024 Reset * Reset by RESET pin * Internal reset by watchdog timer * Reset by power-ON clear circuit * Detection of less than 4.5 VNote (Reset does not occur, however.) * Detection of less than 3.5 VNote (during CPU operation) * Detection of less than 2.3 VNote (in STOP mode) * VDD = 4.5 to 5.5 V (during CPU, PLL operation) * VDD = 3.5 to 5.5 V (during CPU operation) * 80-pin plastic QFP (14 x 20 mm, 0.8-mm pitch) * 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) Supply voltage Package Note These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these. Data Sheet U14126EJ1V0DS00 5 PD178023, 178024 PIN CONFIGURATION (Top View) * 80-pin plastic QFP (14 x 20 mm, 0.8 pitch) PD178023GF-xxx-3B9, 178024GF-xxx-3B9 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 REGOSC REGCPU P125 P124 P123 VDD RESET P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P70/SI3 P71/SO3 P72/SCK3 P73 P74/RXD0 P75/TXD0 P76/SDA0 P77/SCL0 P130/TO50 P131/TO51 P132 P40 P41 P42 GNDPORT VDDPORT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 P122 GND P06 P05 X1 X2 P121 P120 P37 P36/BEEP0 P35 P34/TI51 P33/TI50 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GNDPLL AMIFC FMIFC VDDPLL VCOH VCOL P43 P44 P45 P46 P47 EO0 EO1 IC P50 Cautions 1. Directly connect the IC (Internally Connected) to GND. 2. Keep the voltage at VDDPORT and VDDPLL at the same voltage as VDD. 3. Keep the voltage at GNDPORT and GNDPLL at the same voltage as GND. 4. Connect each of the REGOSC and REGCPU pins to GND via 0.1-F capacitor. 6 Data Sheet U14126EJ1V0DS00 P51 PD178023, 178024 * 80-pin plastic QFP (14 x 14 mm, 0.65 pitch) PD178023GC-xxx-8BT, 178024GC-xxx-8BT P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 REGOSC REGCPU RESET P125 P124 P123 P122 P121 P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P70/SI3 P71/SO3 P72/SCK3 P73 P74/RXD0 P75/TXD0 P76/SDA0 P77/SCL0 P130/TO50 P131/TO51 P132 P40 P41 P42 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 P120 GND P06 P05 VDD X1 X2 P37 P36/BEEP0 P35 P34/TI51 P33/TI50 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDDPORT P43 P44 P45 P46 P47 AMIFC GNDPORT FMIFC VCOH VDDPLL VCOL GNDPLL EO0 EO1 IC P50 P51 P52 Cautions 1. Directly connect the IC (Internally Connected) to GND. 2. Keep the voltage at VDDPORT and VDDPLL at the same voltage as VDD. 3. Keep the voltage at GNDPORT and GNDPLL at the same voltage as GND. 4. Connect each of the REGOSC and REGCPU pins to GND via 0.1-F capacitor. P53 Data Sheet U14126EJ1V0DS00 7 PD178023, 178024 PIN NAME AMIFC ANI0-ANI5 BEEP0 EO0, EO1 FMIFC GND GNDPLL GNDPORT IC P00-P06 P10-P15 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P120-P125 : AM intermediate frequency counter input : A/D converter input : Buzzer output : Error out output : FM intermediate frequency counter input : Ground : PLL ground : Port ground : Internally connected : Port 0 : Port 1 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 12 P130-P132 REGCPU REGOSC RESET RXD0 SCK3 SCL0 SDA0 SI3 SO3 TI50, TI51 TXD0 VDD VDDPLL VDDPORT X1, X2 : Port 13 : Regulator for CPU power supply : Regulator for oscillator : Reset input : Serial (UART0) data input : Serial (SIO3) clock input/output : Serial (IIC0) clock input/output : Serial (IIC0) data input/output : Serial (SIO3) data input : Serial (SIO3) data output : 8-bit timer clock input : Serial (UART0) data output : Power supply : PLL power supply : Port power supply : Crystal resonator INTP0-INTP4 : Interrupt input TO50, TO51 : 8-bit timer output VCOL, VCOH: Local oscillation input 8 Data Sheet U14126EJ1V0DS00 PD178023, 178024 BLOCK DIAGRAM TI50/P33 TO50/P130 TI51/P34 TO51/P131 8-bit TIMER/ EVENT COUNTER50 8-bit TIMER/ EVENT COUNTER51 WATCHDOG TIMER BASIC TIMER 78K/0 CPU CORE ROM PORT0 PORT1 PORT3 7 6 8 8 8 8 8 6 3 6 P00-P06 P10-P15 P30-P37 P40-P47 PORT4 PORT5 PORT6 SI3/P70 SO3/P71 SCK3/P72 SDA0/P76 SCL0/P77 (RXD0)/P74 (TXD0)/P75 INTP0/P00INTP4/P04 BEEP0/P36 5 SERIAL INTERFACE3 I2C BUS P50-P57 P60-P67 P70-P77 P120-P125 P130-P132 ANI0/P10ANI5/P15 AMIFC FMIFC EO0 EO1 VCOL VCOH VDDPLL GNDPLL PORT7 UART0 INTERRUPT CONTROL BUZZER OUTPUT A/D CONVERTER FREQUENCY COUNTER RESET SYSTEM CONTROL CPU PERIPHERAL PLL VOLTAGE REGULATOR PLL PORT12 RAM PORT13 RESET X1 X2 VDDPORT GNDPORT VDD REGOSC REGCPU GND VOLTAGE REGULATOR VOSC VCPU IC Remark The internal ROM and RAM capacities differ depending on the product. Data Sheet U14126EJ1V0DS00 9 PD178023, 178024 CONTENTS 1. PIN 1.1 1.2 1.3 FUNCTION LIST ...................................................................................................................... Port Pins ................................................................................................................................. Pins Other Than Port Pins ................................................................................................... I/O Circuits of Pins and Recommended Connections of Unused Pins ......................... 11 11 12 13 2. MEMORY SPACE ............................................................................................................................ 16 2.1 Memory Size Select Register (IMS) .................................................................................... 17 2.2 Internal Extension RAM Size Select Register (IXS) ......................................................... 18 3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS .......................................................... 3.1 Ports ........................................................................................................................................ 3.2 Clock Generation Circuit ..................................................................................................... 3.3 Timers ..................................................................................................................................... 3.4 Buzzer Output Control Circuit ............................................................................................. 3.5 A/D Converter ........................................................................................................................ 3.6 Serial Interface ...................................................................................................................... 3.7 PLL Frequency Synthesizer ................................................................................................ 3.8 Frequency Counter ............................................................................................................... 19 19 20 20 22 23 24 26 27 4. INTERRUPT FUNCTION ................................................................................................................. 28 5. STANDBY FUNCTION .................................................................................................................... 31 6. RESET FUNCTION ......................................................................................................................... 31 7. INSTRUCTION SET ........................................................................................................................ 32 8. ELECTRICAL SPECIFICATIONS ................................................................................................... 35 9. PACKAGE DRAWING ..................................................................................................................... 44 10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 46 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 47 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 49 10 Data Sheet U14126EJ1V0DS00 PD178023, 178024 1. PIN FUNCTION LIST 1.1 Port Pins Pin Name P00-P04 P05, P06 P10-P15 Input I/O I/O Function Port 0. 7-bit I/O port. Can be set in input or output mode in 1-bit units. Port 1. 6-bit input port. Port 3. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P34 P35 P36 P37 P40-47 I/O Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistors can be specified in software. Interrupt function by key input is provided. Port 5. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. P70 P71 P72 P73 P74 P75 P76 P77 P120-P125 I/O Port 12. 6-bit I/O port. Can be set in input or output mode in 1-bit units. Port 13. 3-bit output port. N-ch open-drain output port (12 V withstand) Input RXD0 TXD0 SDA0 SCL0 -- I/O Port 7. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input SI3 SO3 SCK3 -- Input TI51 -- BEEP0 -- -- At Reset Input Shared by: INTP0-INTP4 -- Input ANI0-ANI5 P30-P32 P33 I/O Input TI50 -- P50-P57 I/O Input -- P60-P67 I/O Input -- P130 P131 P132 Output Low-level output TO50 TO51 -- Data Sheet U14126EJ1V0DS00 11 PD178023, 178024 1.2 Pins Other Than Port Pins Pin Name INTP0-INTP4 I/O Input Function External maskable interrupt input whose valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. Serial data input to serial interface. Serial data output from serial interface. Serial data input/output to/from serial interface. N-ch open drain I/O At Reset Input Shared by: P00-P04 SI3 SO3 SDA0 Input Output I/O Input Input Input P70 P71 P76 SCK3 SCL0 RXD0 TXD0 TI50 TI51 TO50 TO51 BEEP0 ANI0-ANI5 EO0, EO1 I/O Serial clock input/output to/from serial interface. N-ch open drain I/O Input P72 P77 Input Output Input Serial data input to asynchronous serial interface (UART0). Serial data output from asynchronous serial interface (UART0). External count clock input to 8-bit timer (TM50). External count clock input to 8-bit timer (TM51). Input P74 P75 Input P33 P34 Output 8-bit timer (TM50) output. 8-bit timer (TM51) output. Low-level output Input Input - P130 P131 P36 P10-P15 - Output Input Output Buzzer output. Analog input to A/D converter. Error out output from charge pump of PLL frequency synthesizer. VCOL VCOH AMIFC FMIFC RESET X1 X2 REGOSC Input Inputs local oscillation frequency of PLL (in HF and MF modes). Inputs local oscillation frequency of PLL (in VHF mode). - - Input Input to AM intermediate frequency counter. Input to FM or AM intermediate frequency counter. Input - Input Input - - System reset input. Connection of crystal resonator for system clock oscillation. - - - - - - - Regulator for oscillator. Connect this pin to GND via 0.1-F capacitor. Regulator for CPU power supply. Connect this pin to GND via 0.1-F capacitor. Positive power supply. Ground. Port power supply. Port ground. PLL positive power supply. PLL ground. Internally connected. Directly connect this pin to GND. - REGCPU - - - VDD GND VDDPORT GNDPORT VDDPLLNote GNDPLLNote IC - - - - - - - - - - - - - - - - - - - - - Note Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins. 12 Data Sheet U14126EJ1V0DS00 PD178023, 178024 1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins Table 1-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins when they are not used. For the configuration of the I/O circuit of each pin, refer to Figure 1-1. Table 1-1. I/O Circuit Type of Each Pin Pin Name P00/INTP0-P04/INTP4 P05, P06 P10/ANI0-P15/ANI5 P30-P32 P33/TI50 P34/TI51 P35 P36/BEEP0 P37 P40-P47 5-A Set these pins in general-purpose input mode in software, and connect each of them to GND or GNDPORT via resistor. Set these pins in general-purpose input mode in software, and connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor. Set these pins in general-purpose input mode in software, and output low-level signal. Leave unconnected. Set these pins in general-purpose input mode in software, and connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor. 5 25 5 5-K Input I/O I/O Circuit Type 8 I/O I/O Recommended Connection of Unused Pin Set these pins in general-purpose input mode in software, and connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor. Connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor. Set these pins in general-purpose input mode in software, and output low-level signal. Leave unconnected. P50-P57 5 P60-P67 5 P70/SI3 P71/SO3 P72/SCK3 P73 P74/RXD0 P75/TXD0 P76/SDA0 P77/SCL0 P120-P125 P130/TO50 P131/TO51 P132 EO0, EO1 VCOL, VCOH AMIFC, FMIFC 5-K 5 5-K 5 5-K 5 10-D 5 19 Output Set these pins to low-level output in software and leave unconnected. DTS-EO1 DTS-AMP Output Input Leave unconnected. Disable PLL in software and select pull-down. Set these pins in general-purpose input port mode in software and connect each of them to VDD, VDDPORT, GND, or GNDPORT via resistor. REGOSC, REGCPU RESET VDDPLL GNDPLL IC 2 - - Input Connect these pins to GND via 0.1-F capacitor. - Connect this pin to VDD. Directly connect these pins to GND or GNDPORT. - - Data Sheet U14126EJ1V0DS00 13 PD178023, 178024 Figure 1-1. I/O Circuits of Respective Pins (1/2) Type 2 Type 5 VDD Data IN Output disable Input enable N-ch P-ch IN/OUT Schmitt trigger input with hysteresis characteristics Type 5-A VDD Type 5-K VDD Pullup enable Data P-ch VDD P-ch IN/OUT Data P-ch IN/OUT Output disable N-ch Output disable Input enable Type 8 N-ch Input enable Type 10-D VDD Data P-ch IN/OUT P-ch IN/OUT Open drain output disable N-ch VDD Data Output disable N-ch Input enable Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT. 14 Data Sheet U14126EJ1V0DS00 PD178023, 178024 Figure 1-1. I/O Circuits of Respective Pins (2/2) Type 19 Type DTS-EO1 VDDPLL OUT N-ch UP N-ch GNDPLL DW P-ch OUT Type 25 Type DTS-AMP VDDPLL P-ch Comparator + - N-ch VREF (Threshold voltage) IN IN Input enable Note GNDPLL Note This switch is selectable in software only for the VCOL and VCOH pins. Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as VDDPORT and GNDPORT. Data Sheet U14126EJ1V0DS00 15 PD178023, 178024 2. MEMORY SPACE Figure 2-1 shows the memory map of the PD178023, 178024. Figure 2-1. Memory Map FFFFH Special function registers (SFR) 256 x 8 bits FF0 0H FEFFH FEE 0H FEDFH General-purpose registers 32 x 8 bits Internal high-speed RAMNote nnn nH Program area Data memory space 100 0H 0FFFH CALLF entry area Cannot be used 080 0H 07FFH Program area 008 0H 007 FH n n n nH+1 nnn nH Program memory space 000 0H 004 0H 003 FH Internal ROM Note mmm m H mm mm H - 1 CALLT table area Vector table area 000 0H Note The internal ROM and internal high-speed RAM capacities differ depending on the model (refer to the table below). Target Model Name Internal ROM End Address nnnnH 5FFFH 7FFFH Internal High-Speed RAM First Address mmmmH FB00H FB00H PD178023 PD178024 16 Data Sheet U14126EJ1V0DS00 PD178023, 178024 2.1 Memory Size Select Register (IMS) The memory size select register (IMS) sets the internal memory capacity. Set the PD178023, PD178024 to C6H, C8H respectively. Use an 8-bit memory manipulation instruction to set the IMS. This register is set to CFH at reset. Caution Be sure to set the IMS to C6H or C8H as the program initial setting. The IMS set value changes to CFH when reset. Therefore, set C6H or C8H again after reset. Figure 2-2. Format of Memory Size Select Register (IMS) Symbol 7 6 5 4 0 3 2 1 0 Address FFF0H At reset CFH R/W R/W IMS RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 1 Others 1 0 1024 bytes Setting prohibited Selects Internal High-speed RAM Capacity RAM3 RAM2 RAM1 RAM0 0 1 Others 1 0 1 0 0 0 24K bytes 32K bytes Setting prohibited Selects Internal ROM Capacity Table 2-1 indicates the setting of IMS. Table 2-1. Set Value of Memory Size Select Register (IMS) Targeted Model Set Value of IMS C6H C8H PD178023 PD178024 Data Sheet U14126EJ1V0DS00 17 PD178023, 178024 2.2 Internal Extension RAM Size Select Register (IXS) The internal extension RAM size select register (IXS) sets the internal extension RAM capacity. Use the PD178023, PD178024 with the initial value (0CH). Use an 8-bit memory manipulation instruction to set the IXS. This register is set to 0CH at reset. Caution Do not assign a value other than that the value at reset. Figure 2-3. Format of Internal Extension RAM Size Select Register (IXS) Symbol IXS 7 0 6 0 5 0 4 3 2 1 0 Address FFF4H At reset 0CH R/W R/W IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 0 Others 1 1 0 0 0 byte Selects Internal Extension RAM Capacity Setting prohibited Table 2-2 indicates the setting of IXS. Table 2-2. Set Value of Internal Extension RAM Size Select Register Targeted Model Set Value of IXS 0CH PD178023, 178024 18 Data Sheet U14126EJ1V0DS00 PD178023, 178024 3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS 3.1 Ports The following three types of ports are available: * CMOS input (port 1) * N-ch open-drain output (port 13) Total : : 6 pins 3 pins * CMOS I/O (ports 0, 3 - 7, and 12) : 53 pins : 62 pins Table 3-1. Port Functions Name Port 0 Port 1 Port 3 Port 4 Port 5 Port 6 Port 7 Port 12 Port 13 Pin Name P00-P06 P10-P15 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P120-P125 P130-P132 Function I/O port. Can be set in input or output mode in 1-bit units. Input-only port I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. I/O port. Can be set in input or output mode in 1-bit units. N-ch open-drain output port Data Sheet U14126EJ1V0DS00 19 PD178023, 178024 3.2 Clock Generation Circuit The instruction execution time can be changed as follows: * 0.45 s/0.89 s/1.78 s/3.56 s/7.11 s (system clock: 4.5-MHz crystal resonator) Note Figure 3-1. Block Diagram of Clock Generation Circuit Prescaler X1 X2 System clock oscillator Clock to other than peripheral hardware fX Prescaler Selector fX fX 4 fX 23 2 fX 22 2 Standby control circuit Wait control circuit CPU clock (fCPU) 3 STOP 0 0 0 0 0 PCC2 PCC1 PCC0 Processor clock control register (PCC) Internal bus 3.3 Timers Four timer channels are provided. * Basic timer * Watchdog timer : 1 channel : 1 channel Figure 3-2. Block Diagram of Basic Timer * 8-bit timer/event counter : 2 channels 4.5 MHz Divider circuit INTBTM0 20 Data Sheet U14126EJ1V0DS00 PD178023, 178024 Figure 3-3. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus Mask circuit 8-bit compare register 50 (CR50) Selector INTTM50 TI50/P33 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Coincidence Selector 8-bit counter 50 OVF (TM50) Selector S Q INV R TO50/P130 Output latch (P130) Clear 3 Selector S R Level inversion TCL502 TCL501 TCL500 Timer clock select register 50 (TCL50) TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50 Timer mode control register 50 (TMC50) Internal bus Figure 3-4. Block Diagram of 8-Bit Timer/Event Counter 51 Internal bus Mask circuit 8-bit compare register 51 (CR51) Selector INTTM51 TI51/P34 fX/2 fX/23 fX/25 fX/27 fX/29 fX/211 Coincidence Selector 8-bit counter 51 OVF (TM51) Selector S Q INV R TO51/P131 Output latch (P131) Clear 3 Selector S R Level inversion TCL512 TCL511 TCL510 Timer clock select register 51 (TCL51) TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51 Timer mode control register 51 (TMC51) Internal bus Data Sheet U14126EJ1V0DS00 21 PD178023, 178024 Figure 3-5. Block Diagram of Watchdog Timer fX/28 Clock input control circuit Divider circuit Divided clock select circuit INTWDT Output control circuit RESET RUN Division mode select circuit 3 WDT mode signal OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) WDCS2 WDCS1 WDCS0 RUN WDTM4 WDTM3 Watchdog timer clock select register (WDCS) Internal bus Watchdog timer mode register (WDTM) 3.4 Buzzer Output Control Circuit The buzzer output frequency is selected as follows. * BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz Figure 3-6. Block Diagram of Buzzer Output Control Circuit (BEEP0) 1 kHz 1.5 kHz 3 kHz 4 kHz Selector BEEP0/P36 Output latch (P36) PM36 BEEP BEEP BEEP BEEP0 clock select CL02 CL01 CL00 register (BEEPCL0) Internal bus 22 Data Sheet U14126EJ1V0DS00 PD178023, 178024 3.5 A/D Converter An A/D converter with a resolution of 8 bits x 6 channels is provided. Figure 3-7. Block Diagram of A/D Converter ANI0/P10 Selector Tap selector ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 Sample & hold circuit Voltage comparator VDD ADCS3 Successive approximation register (SAR) GND Control circuit Control circuit INTAD3 Voltage comparator Power-fail comparison threshold value register 3 (PFT3) 4 A/D conversion result register 3 (ADCR3) ADS33 ADS32 ADS31 ADS30 ADCS3 0 FR32 FR31 FR30 0 0 0 PFEN3 PFCM3 PFHRM3 Analog input channel specification register 3 (ADS3) A/D converter mode register 3 (ADM3) Power-fail comparison mode register 3 (PFM3) Internal bus Data Sheet U14126EJ1V0DS00 23 PD178023, 178024 3.6 Serial Interface The PD178023 and 178024 have three serial interface channels. * Serial interface (IIC0) * Serial interface (SIO3) * Serial interface (UART0) Figure 3-8. Block Diagram of Serial Interface (IIC0) Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) SDA0/P76 Noise elimination circuit Slave address register 0 (SVA0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Coincidence CLEAR signal SET SO0 latch IIC shift register 0 DQ (IIC0) CL01, CL00 N-ch opendrain output Data hold time correction circuit ACK detection circuit Wake up control circuit ACK detection circuit Start condition detection circuit SCL0/P77 Noise elimination circuit Stop condition detection circuit Interrupt request signal generator Serial clock counter INTIIC0 Serial clock control circuit Serial clock wait control circuit fX Prescaler CLD0 DAD0 SMC0 DFC0 CL01 CL00 IIC transfer clock select register 0 (IICCL0) Internal bus 24 Data Sheet U14126EJ1V0DS00 PD178023, 178024 Figure 3-9. Block Diagram of Serial Interface (SIO3) Internal bus 8 SI3/P70 PM71 SO3/P71 SCK3/P72 P71 output latch Serial clock counter Serial clock control circuit PM72 P72 output latch Interrupt request signal generation circuit INTCSI3 4 Serial I/O shift registe 3 (SIO3) Selector fX/25 fX/2 fX/26 Figure 3-10. Block Diagram of Serial Interface (UART0) Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) RXD0/P74 Receive shift register 0 (RX0) PE0 FE0 OVE0 Transmit shift register 0 (TXS0) TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 0 TXD0/P75 Reception control circuit PM75 (parity check) P75 output latch INTSER0 INTSR0 Transmission control circuit (parity append) INTST0 Baud rate generator fX/2-fX/28 Data Sheet U14126EJ1V0DS00 25 PD178023, 178024 3.7 PLL Frequency Synthesizer Figure 3-11. Block Diagram of PLL Frequency Synthesizer Internal Bus PLL Mode Select Register (PLLMD) VCOH VCOL PLL PLL DMD DMD MD1 MD0 2 VCOH Mixer VCOL Input Select Block Programmable Divider PLL Data Transfer Register (PLLNS) PLL Data Register (PLLRL, PLLRH, PLLR0) 2 fN Phase Comparator ( -DET) Charge Pump EO0 EO1 PLL NS0 fr Voltage Control Generator Note 4.5 MHz Reference Frequency Generator Unlock F/F 4 Note Lowpass Filter PLL PLL PLL PLL PLL RF3 RF2 RF1 RF0 UL0 PLL Reference PLL Unlock F/F Judge Register Mode Register (PLLUL) (PLLRF) Internal Bus Note External circuit. 26 Data Sheet U14126EJ1V0DS00 PD178023, 178024 3.8 Frequency Counter Figure 3-12. Block Diagram of Frequency Counter 2 Gate time control block FMIFC Input select block AMIFC Start/stop control block IF counter register (IFC) block 2 IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF counter mode select register (IFCMD) IF counter gate judge register (IFCJG) IFC JG0 IFC IFC ST RES IF counter control register (IFCCR) Internal bus Data Sheet U14126EJ1V0DS00 27 PD178023, 178024 4. INTERRUPT FUNCTION The PD178023 and 178024 have the following three types and 17 sources of interrupts: * Non-maskable : 1Note * Maskable * Software Note : 16Note :1 Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and either of them can be selected. Table 4-1. Interrupt Sources Interrupt Source Name INTWDT Trigger Overflow of watchdog timer (when watchdog timer mode 1 is selected) Overflow of watchdog timer (when interval timer mode is selected) Pin input edge detection External 0006H 0008H 000AH 000CH 000EH Detection of key input of port 4 End of transfer by serial interface IIC0 Internal 0010H 0012H 0014H 0016H - Internal 0018HNote 3 001AH 001CH (B) - (B) Vector Table Address 0004H Basic Configuration TypeNote 2 (A) Interrupt Type Default PriorityNote 1 - Internal/ External Internal Non-maskable Maskable 0 INTWDT (B) 1 2 3 4 5 6 7 8 9 10 11 12 INTP0 INTP1 INTP2 INTP3 INTP4 INTKY INTIIC0 (C) INTBTM0 Generation of basic timer match signal INTAD3 - INTCSI3 INTTM50 End of conversion by A/D converter - End of transfer by serial interface SIO3 Generation of coincidence signal of 8-bit timer/event counter 50 13 INTTM51 Generation of coincidence signal of 8-bit timer/event counter 51 001EH 14 15 16 Software - INTSER0 Reception error of serial interface UART0 INTSR0 INTST0 BRK End of reception by serial interface UART0 End of transmission by serial interface UART0 Execution of BRK instruction - 0020H 0022H 0024H 003EH (D) Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending according to their default priorities. The default priority 0 is the highest, while 16 is the lowest. 2. (A) to (D) under the heading Basic Configuration Type corresponds to (A) to (D) in Figure 4-1. 3. There are no interrupt sources corresponding to vector addresses 0018H. 28 Data Sheet U14126EJ1V0DS00 PD178023, 178024 Figure 4-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Priority control circuit Vector table address generation circuit Standby release signal (B) Internal maskable interrupt Internal bus MK IE PR ISP Interrupt request IF Priority control circuit Vector table address generation circuit Standby release signal (C) External maskable interrupt Internal bus External interrupt rising/ falling edge enable registers (EGP, EGN) MK IE PR ISP Interrupt request Edge detection circuit IF Priority control circuit Vector table address generation circuit Standby release signal Data Sheet U14126EJ1V0DS00 29 PD178023, 178024 Figure 4-1. Basic Configuration of Interrupt Function (2/2) (D) Software interrupt Internal bus Interrupt request Priority control circuit Vector table address generation circuit Remark IF IE : Interrupt request flag : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 30 Data Sheet U14126EJ1V0DS00 PD178023, 178024 5. STANDBY FUNCTION There are the following two standby functions to reduce the system power consumption. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operating mode. * STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and current consumption can be considerably reduced. Figure 5-1. Standby Function System Clock Operation STOP Instruction Interrupt Request HALT Mode (Clock supply to CPU is stopped, oscillation continued) HALT Instruction Interrupt Request STOP Mode (System clock oscillation stopped) 6. RESET FUNCTION There are the following three reset methods. * External reset input by RESET pin * Internal reset by watchdog timer runaway time detection * Internal reset by Power-On Clear (POC). Data Sheet U14126EJ1V0DS00 31 PD178023, 178024 7. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand First Operand A #byte A r [HL + byte] Note sfr saddr !addr16 PSW [DE] [HL] [HL + B] [HL + C] $addr16 1 None ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV INC DEC B,C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV DBNZ DBNZ INC DEC !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV MOV MOV PUSH POP ROR4 ROL4 MOV MOV MULU DIVUW Note Except r = A 32 Data Sheet U14126EJ1V0DS00 PD178023, 178024 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX #word ADDW SUBW CMPW MOVW AX rp Note MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None rp MOVW Note INCW DECW PUSH POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW Note Only when rp = BC, DE or HL Data Sheet U14126EJ1V0DS00 33 PD178023, 178024 (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1 sfr.bit MOV1 saddr.bit MOV1 PSW.bit MOV1 [HL].bit MOV1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 (4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 34 Data Sheet U14126EJ1V0DS00 PD178023, 178024 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage Symbol VDD VDDPORT VDDPLL Input voltage Output voltage Output breakdown voltage Analog input voltage High-level output current VI VO VBDS Excluding P130 to P132 P130-P132 N-ch open drain Conditions Rating -0.3 to +6.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +11.0 -0.3 to VDD + 0.3 16 Unit V V V V V V VAN IOH P10-P15 1 pin Analog input pin -0.3 to VDD + 0.3 -8 -15 V mA mA Total of P00-P06, P30-P37, P54-P57, P60-P67, and P120-P125 Total of P40-P47, P50-P53, and P70-P77 -15 16 8 30 15 mA mA mA mA mA C C Low-level output current IOL Note 1 pin Peak value r.m.s Total of P00-P06, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P120-P125, and P130-P132 Operating temperature Storage temperature TA Tstg Peak value r.m.s -40 to +85 -55 to +125 Note Calculate the r.m.s as follows: [r.m.s] = [Peak value] x Duty Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, are the values exceeding which the product may be physically damaged. Be sure to use the product with these ratings never being exceeded. Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. Recommended Supply Voltage Ranges (TA = -40 to +85 C) Parameter Supply voltage Symbol VDD1 VDD2 Data retention voltage Output breakdown voltage VDDR VBDS Conditions When CPU and PLL are operating When CPU is operating and PLL is stopped When crystal oscillation stops P130-P132 (N-ch open drain) MIN. 4.5 3.5 2.3 TYP. 5.0 5.0 MAX. 5.5 5.5 5.5 15 Unit V V V V Data Sheet U14126EJ1V0DS00 35 PD178023, 178024 DC Characteristics (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (1/2) Parameter High-level input voltage Symbol VIH1 Test Conditions P10-P15, P30-P32, P35-P37, P40-P47, P50-P57, P60-P67, P71, P73, P120-P125 P00-P06, P33, P34, P70, P72, P74-P75, RESET P76, P77 (N-ch open-drain I/O) 4.5 V VDD 5.5 V MIN. 0.7 VDD TYP. MAX. VDD Unit V VIH2 VIH3 0.8 VDD 0.7 VDD VDD VDD V V Low-level input voltage VIL1 P10-P15, P30-P32, P35-P37, P40-P47, P50-P57, P60-P67, P71, P73, P120-P125 P00-P06, P33, P34, P70, P72, P74-P75, RESET P76, P77 (N-ch open-drain I/O) P00-P06, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P120-P125 4.5 V VDD 5.5 V 4.5 V VDD 5.5 V, IOH = -1 mA 3.5 V VDD < 4.5 V, IOH = -100 A VDD = 4.5 to 5.5 V, IOH = -3 mA 4.5 V VDD 5.5 V, IOL = 1 mA 3.5 V VDD < 4.5 V, IOL = 100 A VDD = 4.5 to 5.5 V, IOL = 3 mA 4.5 V VDD 5.5 V IOL = 3 mA 4.5 V VDD 5.5 V IOL = 6 mA 0 0.3 VDD V VIL2 VIL3 0 0 0.2 VDD 0.3 VDD V V High-level output voltage VOH1 VDD - 1.0 V VDD - 0.5 V VOH2 EO0, EO1 VDD - 1.0 V Low-level output voltage VOL1 P00-P06, P30-P37, P40-47, P50-57, P60-P67, P70-P75, P120-P125 1.0 V 0.5 V VOL2 EO0, EO1 1.0 VOL3 P76, P77 (N-ch open-drain I/O) 0.4 V 0.6 V High-level input leakage current ILH P00-P06, P30-P37, P50-P57, P70-P77, RESET P10-P15, P40-P47, P60-P67, P120-P125, VIN = VDD 3 A Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. 36 Data Sheet U14126EJ1V0DS00 PD178023, 178024 DC Characteristics (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (2/2) Parameter Low-level input leakage current Symbol ILIL P00-P06, P30-P37, P50-P57, P70-P77, RESET Test Conditions P10-P15, P40-P47, P60-P67, P120-P125, VIN = 0 V MIN. TYP. MAX. -3 Unit A Output off leakage current ILOH1 ILOL1 ILOH2 P130-P132 P130-P132 P76, P77 (at N-ch open drain I/O) P76, P77 (at N-ch open drain I/O) EO0, EO1 EO0, EO1 VOUT = 15 V VOUT = 0 V VOUT = VDD -3 3 -3 A A A A A A mA ILOL2 VOUT = 0 V 3 ILOH3 ILOL3 Supply currentNote IDD1 VOUT = VDD VOUT = 0 V 4.0 -3 3 20 When CPU is operating and PLL is stopped. Sine wave input to X1 pin At fX = 4.5 MHz VIN = VDD In HALT mode with PLL stopped. Sine wave input to X1 pin At fX = 4.5 MHz VIN = VDD When crystal resonator is oscillating When crystal oscillation is stopped Power-failure detection function Data memory retained When crystal oscillation is stopped TA = 25 C, VDD = 5 V 3.5 2.2 IDD2 0.35 0.70 mA Data retention voltage VDDR1 VDDR2 5.5 V V VDDR3 Data retention current IDDR2 IDDR1 2.0 2.0 4.0 V A A 2.0 20 Note Excluding AVDD current and VDDPLL current. Remarks 1. fX: System clock oscillation frequency 2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the corresponding port pin. Data Sheet U14126EJ1V0DS00 37 PD178023, 178024 Reference Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Supply current Symbol IDD3 Conditions When CPU and PLL are operating. Sine wave input to VCOH pin At fIN = 160 MHz VIN = 0.15 VP-P MIN. TYP. 8 MAX. Unit mA AC Characteristics (1) Basic operation (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) Parameter Cycle time (minimum instruction execution time) TI50, TI51 input frequency TI50, TI51 input high-/low-level widths Interrupt input high-/low-level widths RESET pin low-level width Symbol TCY fX = 4.5 MHz Conditions MIN. 0.44 TYP. MAX. 7.11 Unit s fTI5 2 MHz tTIH5 tTIL5 tINTH tINTL tRSL INTP0-INTP4 200 ns 1 s s 10 38 Data Sheet U14126EJ1V0DS00 PD178023, 178024 (2) Serial interface (TA = -40 to +85 C, VDD = 3.5 to 5.5 V) (a) Serial interface (IIC0) I2C bus mode Parameter Symbol Standard Mode MIN. SCL0 clock frequency Bus free time (between stop and start conditions) Hold timeNote 1 SCL0 clock low-level width SCL0 clock high-level width Start/restart condition setup time Data hold time CBUS compatible master I 2C bus tSU : DAT tR tF tSU : STO tSP Cb fCLK tBUF 0 4.7 MAX. 100 - High-speed Mode MIN. 0 1.3 MAX. 400 - kHz Unit s s s s s s s ns ns ns tHD : STA tLOW tHIGH tSU : STA tHD : DAT 4.0 4.7 4.0 4.7 5.0 0Note 2 250 - - 4.0 - - - - - - - - - 1000 300 - - 400 0.6 1.3 0.6 0.6 - 0Note 2 100Note 4 20+0.1CbNote 5 20+0.1CbNote 5 0.6 0 - - - - - - 0.9Note 3 - 300 300 - 50 400 Data setup time SDA0 and SCL0 signal rise time SDA0 and SCL0 signal fall time Stop condition setup time Pulse width of spike restrained by input filter Each bus line capacitative load s ns pF Notes 1. The first clock pulse is generated at the start condition after this period. 2. The device needs to internally supply a hold time of at least 300 ns for the SDA0 signal to fill the undefined area at the falling edge of the SCL0 (VIHmin. of the SCL0 signal). 3. Unless the device extends the low hold time (tLOW) of the SCL0 signal, it is necessary to fill only the maximum data hold time (tHD : DAT). 4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy the following conditions: * When the device does not extend the low hold time of the SCL0 signal tSU : DAT 250 ns * When the device extends the low hold time of the SCL0 signal Send the next data bit to the SDA line before releasing the SCL0 line (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns : in the standard mode I2C bus specification) 5. Cb: Total capacitance of one bus line (unit: pF) Data Sheet U14126EJ1V0DS00 39 PD178023, 178024 (b) Serial interface (SIO3) (i) 3-wire serial I/O mode (SCK3 ... internal clock output) Parameter SCK3 cycle time SCK3 high/low-level width Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 C = 100 pF Note Test Conditions MIN. 800 tKCY1/2 - 50 TYP. MAX. Unit ns ns SI3 setup time (to SCK3) SI3 hold time (from SCK3) SCK3 SO3 output delay time 100 400 300 ns ns ns Note C is the load capacitance of SCK3 and SO3 output line. (ii) 3-wire serial I/O mode (SCK3 ... external clock input) Parameter Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 tR2, tF2 C = 100 pF Note Test Conditions MIN. 800 400 TYP. MAX. Unit ns ns SCK3 cycle time SCK3 high/low-level width SI3 setup time (to SCK3) SI3 hold time (from SCK3) SCK3 SO3 output delay time SCK3 at rising or falling edge time 100 400 300 1000 ns ns ns ns Note C is the load capacitance of SO3 output line. (d) Serial interface (UART0: Dedicated baud rate generator output) Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 38400 Unit bps 40 Data Sheet U14126EJ1V0DS00 PD178023, 178024 AC Timing Test Point (Excluding X1 Input) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD TI Timing 1/fTI5 tTIL5 tTIH5 TI50,TI51 Interrupt Input Timing tINTL tINTH INTP0 to INTP4 RESET Input Timing tRSL RESET Data Sheet U14126EJ1V0DS00 41 PD178023, 178024 Serial Transfer Timing I2C bus mode: tLOW SCL0 tHD : DAT tHD : STA tR tHIGH tSU : DAT tF tSU : STA tHD : STA tSP tSU : STO SDA0 tBUF Stop condition Start condition Restart condition Stop condition 3-wire serial I/O mode: tKCYm tKLm tRn SCK3 tSIKm tKSIm tKHm tFn SI3 tKSOm Input Data SO3 Output Data Remark m = 1, 2 n=2 42 Data Sheet U14126EJ1V0DS00 PD178023, 178024 A/D Converter Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Resolution Total conversion errorNote Conversion time Analog input voltage tCONV VIAN 15.2 0 Symbol Conditions MIN. 8 TYP. 8 MAX. 8 0.8 Unit bit % 45.7 VDD s V Note Excluding quantization error (1/2LSB) PLL Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN1 fIN2 fIN3 fIN4 Conditions VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P MIN. 0.5 10 60 40 TYP. MAX. 3.0 40 130 160 Unit MHz MHz MHz MHz IFC Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN5 Test Conditions AMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, FMIF count mode, sine wave input, VIN = 0.15 VP-P FMIFC pin, AMIF count mode, sine wave input, VIN = 0.15 VP-P MIN. 0.4 TYP. MAX. 0.5 Unit MHz fIN6 10 11 MHz fIN7 0.4 0.5 MHz Data Sheet U14126EJ1V0DS00 43 PD178023, 178024 9. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x20) A B 64 65 41 40 detail of lead end S CD Q R 80 1 25 24 F G H I M J P K M N S L S NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 1.0 0.8 0.37 +0.08 -0.07 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.17 +0.08 -0.07 0.10 2.70.1 0.10.1 55 3.0 MAX. P80GF-80-3B9-5 44 Data Sheet U14126EJ1V0DS00 PD178023, 178024 80-PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end S C D R Q 80 1 21 20 F J G P H I M K S N S L M ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.200.20 14.000.20 14.000.20 17.200.20 0.825 0.825 0.320.06 0.13 0.65 (T.P.) 1.600.20 0.800.20 0.17 +0.03 -0.07 0.10 1.400.10 0.1250.075 3 +7 -3 1.70 MAX. P80GC-65-8BT-1 NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. Data Sheet U14126EJ1V0DS00 45 PD178023, 178024 10. RECOMMENDED SOLDERING CONDITIONS Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Table 10-1. Soldering Conditions for Surface-Mount Type PD178023GF-XXX-3B9: 80-pin plastic QFP (14 x 20 mm, 0.8-mm pitch) PD178024GF-XXX-3B9: 80-pin plastic QFP (14 x 20 mm, 0.8-mm pitch) Recommended Conditions Symbol Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C, Time: 30 sec max. (210 C min.), IR35-00-3 Number of times: 3 max. Package peak temperature: 215 C, Time: 40 sec max. (200 C min.), VP15-00-3 Number of times: 3 max. Solder bath temperature: 260 C max., Time: 10 sec max., Number of times: 1, Preheating temperature: 120 C max., (Package surface temperature) Pin temperature: 300 C max., Time: 3 sec max (per device side) WS60-00-1 VPS Wave soldering Partial heating - Caution Do not use two or more soldering methods in combination (except partial heating). PD178023GC-XXX-8BT: 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) PD178024GC-XXX-8BT: 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) Recommended Conditions Symbol Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235 C, Time: 30 sec max. (210 C min.), IR35-00-2 Number of times: 2 max. Package peak temperature: 215 C, Time: 40 sec max. (200 C min.), VP15-00-2 Number of times: 2 max. Solder bath temperature: 260 C max., Time: 10 sec max., Number of times: 1, Preheating temperature: 120 C max., (Package surface temperature) Pin temperature: 300 C max., Time: 3 sec max (per device side) WS60-00-1 VPS Wave soldering Partial heating - Caution Do not use two or more soldering methods in combination (except partial heating). 46 Data Sheet U14126EJ1V0DS00 PD178023, 178024 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD178023, 178024 subseries. (1) Language processor software RA78K0Notes 1, 2, 3 CC78K0Notes 1, 2, 3 DF178124Notes 1, 2, 3 CC78K0-LNotes 1, 2, 3 Assembler package common to 78K/0 series C compiler package common to 78K/0 series Device file for PD178024 subseries C compiler library source file common to 78K/0 series (2) Flash memory writing tools Fashpro III (Part number: FL-PR3Note 4, PG-FL3) FA-80GFNote 4 FA-80GC-8BTNote 4 Dedicated flash writer Flash memory writing adapter (3) Debugging tools * When in-circuit emulator IE-78K0-NS is used IE-78K0-NS IE-70000-MC-PS-B IE-78K0-NS-PANote 5 IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Power supply unit for IE-78K0-NS Performance board for enhancing and expanding the IE-78K0-NS function Interface adapter necessary when a PC-9800 series (except notebook-type PC) is used as host machine (C bus supported) PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA socket supported) IE-70000-PC-IF-C IE-70000-PCI-IF IE-178134-NS-EM1Note 5 NP-80GFNote 4 EV-9200G-80 NP-80GCNote 4 EV-9200GC-80 SM78K0Notes 1, 2 ID78K0-NSNotes 1, 2 DF178124Notes 1, 2, 3 Interface adapter when a IBM PC/ATTM compatible machine is used (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Emulation board for emulating the PD178024 subseries Emulation probe for 80-pin plastic QFP (GF-3B9 type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GF-3B9 type) Emulation probe for 80-pin plastic QFP (GC-8BT type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178024 subseries IE-70000-CD-IF-A Notes 1. PC-9800 series (MS-DOSTM + WindowsTM) based 2. IBM PC/AT compatible machine (Japanese/English Windows) based 3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM (NEW-OSTM) based 4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813). Consult NEC distributor when purchasing these products. 5. Under development Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178124. Data Sheet U14126EJ1V0DS00 47 PD178023, 178024 * When in-circuit emulator IE-78001-R-A is used IE-78001-R-A IE-70000-98-IF-C In-circuit emulator common to 78K/0 series Interface adapter necessary when a PC-9800 series (except notebook-type PC) is used as host machine (C bus supported) Interface adapter when a IBM PC/AT compatible machine is used (ISA bus supported) Interface adapter necessary when a PC with a PCI bus is used as host machine Interface adapter and cable necessary when an EWS is used as host machine Emulation board for emulating the PD178024 subseries Emulation probe conversion board necessary when using IE-178134-NS-EM1 on IE-78001-R-A. Emulation probe for 80-pin plastic QFP (GF-3B9 type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GF-3B9 type) Emulation probe for 80-pin plastic QFP (GC-8BT type) Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-8BT type) System simulator common to 78K/0 series Integrated debugger common to 78K/0 series Device file for PD178024 subseries IE-70000-PC-IF-C IE-70000-PCI-IF IE-78000-R-SV3 IE-178134-NS-EM1Note4 IE-78K0-R-EX1 EP-78130GF-R EV-9200G-80 EP-78230GC-R EV-9200GC-80 SM78K0Notes 1, 2 ID78K0Notes 1, 2 DF178124Notes 1, 2, 3 Real-time OS RX78K0Notes 1, 2, 3 MX78K0Notes 1, 2, 3 Real-time OS for 78K/0 series OS for 78K/0 series Notes 1. PC-9800 series (MS-DOS + Windows) based 2. IBM PC/AT compatible machine (Japanese/English windows) based 3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEW-OS) based 4. Under development Remark Use SM78K0 in combination with the DF178124. 48 Data Sheet U14126EJ1V0DS00 PD178023, 178024 APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Device Documents Title Document No. Japanese English This document U13915E U12326E -- -- U12704E PD178023, 178024 Data Sheet PD178024, 178124 Subseries User's Manual 78K/0 Series User's Manual--Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table 78K/0 Series Application Note Basics (I) U14126J U13915J U12326J U10904J U10903J U12704J Development Tool Documents (User's Manual) Title RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language RA78K Series Structured Assembler Preprocessor CC78K0 C Compiler Operation Language IE-78001-R-A IE-78K0-NS IE-178134-NS-EM1 EP-78230 EP-78130 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User Open Interface Specifications Reference Reference Guide Reference U12323J U11517J U11518J To be prepared U13731J To be prepared EEU-985 - U10181J U10092J EEU-1402 U11517E U11518E To be prepared To be prepared To be prepared EEU-1515 EEU-1470 U10181E U10092E U11802J U11801J U11789J Document No. Japanese English U11802E U11801E U11789E ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based ID78K0 Integrated Debugger Windows Based ID78K0-NS Integrated Debugger Windows Based U11151J U11539J U11649J U12900J - U11539E U11649E U12900E Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc. Data Sheet U14126EJ1V0DS00 49 PD178023, 178024 Related Documents for Embedded Software (User's Manual) Title 78K/0 Series Real-time OS Fundamental Installation 78K/0 Series OS MX78K0 Fundamental U11537J U11536J U12257J Document No. Japanese English U11537E U11536E U12257E Other Documents Title SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality/Reliability Handbook Microcomputer Product Series Guide X13769X C10535J C11531J C10983J C11892J C12769J U11416J C10535E C11531E C10983E C11892E -- -- Document No. Japanese English Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc. 50 Data Sheet U14126EJ1V0DS00 PD178023, 178024 [MEMO] Data Sheet U14126EJ1V0DS00 51 PD178023, 178024 [MEMO] 52 Data Sheet U14126EJ1V0DS00 PD178023, 178024 [MEMO] Data Sheet U14126EJ1V0DS00 53 PD178023, 178024 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. IEBus is a trademark of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. 54 Data Sheet U14126EJ1V0DS00 PD178023, 178024 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U14126EJ1V0DS00 55 PD178023, 178024 The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. * The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M5 98.8 |
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